Exemplary embodiments of the present invention relate to a delay locked loop (DLL) used in a semiconductor integrated circuit.
A semiconductor integrated circuit such as various logic operation devices, CPUs, and memory devices includes a logic circuit which processes data. In order to normally process data, a logic circuit of a semiconductor integrated circuit may operate in synchronization with a reference signal outputted from an oscillator. Here, a semiconductor integrated circuit may include a delay locked loop which synchronizes a clock signal outputted from an oscillator with an operation clock of a logic circuit.
A typical delay locked loop includes a delay line having a plurality of unit delay cells coupled in series. The delay line becomes longer as the delay range of the delay locked loop increases. In other words, the number of unit delay cells coupled in series increases linearly in proportion to expansion of the delay range (that is, delay amount) of the delay locked loop.
In addition, the delay locked loop may include a selection circuit which selects any one of signals delayed by the delay line. The selection circuit has as many input passages as the expansion of the delay range. In other words, as the delay range expands, the selection circuit becomes complicated.
Therefore, the delay locked loop may have difficulty in expanding the delay range and have a complicated circuit configuration in proportion to the magnitude of the delay range. Furthermore, the delay locked loop may occupy a larger area as the delay range expands, causing difficulty in a circuit layout of a semiconductor integrated circuit.